AppleInsider -
15 Jul 2020 16:19

JEDEC, the controlling body of the RAM standard, has published details about the DDR5 SDRAM spec to address the demand for ever-faster RAM. The new DDR5 spec is designed to enable scaling memory performance without degrading channel efficiency at higher speeds. This was done by doubling the burst-length to BL16 and bank-count to 32 from 16. DDR5 DIMM also has two 40-bit independent sub-channels, increasing efficiency, and reliability.A new feature deemed Decision Feedback Equalization (DFE) enab...
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